FIG. 11 shows a conventional channel driver circuit of PWM through system.
Reference numeral 1 denotes a timing pulse generator on side A that generates a pulse for driving an output transistor from an input pulse INA. Reference numeral 2 denotes an output driver circuit on side A. Reference numeral 3 denotes a load. Reference numeral 5 denotes a timing pulse generator on side B that generates a pulse for driving an output transistor from an input pulse INB. Reference numeral 4 denotes an output driver circuit on side B.
The output driver circuit 2 is configured as shown in FIG. 12.
Reference numerals 11, 12, 14, and 15 denote resistors or current sources for determining a speed of charging/discharging the gates of output transistors 41 and 42. Reference numerals 31 and 34 denote P-type switch transistors for determining, based on pulses AF− and AD− from the timing pulse generator 1, timing of charging the gates of the output transistors 41 and 42. Reference numerals 32, 33, 35, and 36 denotes N-type switch transistor for determining, based on pulses AE, AF, AG, and AD from the timing pulse generator 1, timing of discharging the gates of the output transistors 41 and 42. Reference numerals 51 and 52 denote diodes for imposing a limit in such a way that a reverse voltage between the gate and source of the output transistor 41 on the upper side does not exceed the withstand voltage of the output transistor 41. Side B has completely the same configuration as side A.
FIG. 13 is a timing chart for driving the output driver circuit 2 of FIG. 12. Side B has completely the same configuration as side A.
As shown in FIG. 13, delay pulses indicated by AD and AD− and delay pulses indicated by AF and AF− are generated from the input pulse INA to provide dead times d1 and d2, thereby preventing a shoot-through current. As shown in FIG. 13, because of the presence of the dead times d1 and d2, the waveform of an output FO differs according to the voltage of an output terminal RO on side B. The functions of the dead times d1 and d2 include a buffer or a level shift, in which the input pulse is outputted as it is to an output terminal. The load 3 of the output is a resistor, a coil, and so on. Such a configuration is disclosed in Japanese Patent Laid-Open No. 6-90589 and so on.
It is an object of the conventional art to prevent a shoot-through current and obtain a desired output slew rate and preferred linearity when an output voltage changes in a driver circuit used for a channel driver and so on.
A shoot-through current poses a significant danger because a large current flows from a power supply to the ground and generates heat. Further, an extremely high output slew rate causes extraneous radiation and an extremely low output slew rate results in an endless change of an output waveform during the dead time and causes a shoot-through current.
Regarding linearity, the dead time reduces a gain and degrades linearity when a duty difference is small between PWM input pulses on both sides, that is, in an area where a small current passes through the load 3. Such a phenomenon makes it difficult to finely control the load 3 of an actuator and so on.